Vitesse zeros in on carrier-Ethernet switch needs

The explosion of interest in CE (carrier Ethernet) seems to be at the front of everyone’s mind these days. In case you haven’t been following the networking market lately, the basic story is this: Just as wireless service providers and conventional telephone-service providers decided to evolve from their legacy switched networks and synchronous rings into Internet-compatible packet networks, they faced a coincidence of three massive trends: the explosion of data traffic in cellular networks, the allure of delivering high-definition television through IP (Internet Protocol) packets to homes, and the rumor of a huge shift toward cloud computing.

The result for both wireless backhaul networks and the wired infrastructure behind all those DSL (digital-subscriber-line) and cable connections was the same. The providers want a packet-based network with enormous bandwidth—such as enterprise Ethernet—but with all the features these providers had from their legacy networks. These services include awareness of the service needs of each flow through the switch, multicast capability, carrier-class reliability and management functions, and support for precise timing. Carriers also want to provide guaranteed QOS (quality of service) for media types such as voice and high-definition video. The answer to all these desires, the industry claims, is CE.

The next question is how to implement CE in a way that can be both fast and cheap. Service providers are blowing right past 40-Gbit switches and asking for 100-Gbit capability, but they are severely financially constrained. The obvious solution is to start with a fast enterprise switch and enhance it to provide the additional services. This approach runs into problems, however.

If your enterprise switch relies on NPUs (network-processing units), you can simply add to the NPU software, but you will almost certainly run out of processing power long before you get all the new features in, even at low wire speeds. If your switch uses an ASSP (application-specific standard product) or an ASIC, it won’t be flexible. Either way, you will have to add another ASIC or, more likely, an FPGA or two to the design, running up the BOM (bill-of-materials) cost, power, and design time.

And, as Morteza Ghodrat, director of CE technology at Vitesse Semiconductor, is quick to point out, adding more packet-processing sites to the design means adding more DRAMs and CAMs (content-addressable memories). Either you put duplicate memory chips around each chip, or you attempt some sort of shared-memory pool with the obvious complications.

To address these problems, Vitesse recently announced three MAC (media-access-controller) and switch chips. Ghodrat argues that all CE services interrelate both architecturally and in efficiency; thus, a single architecture rather than multiple chips should handle them. The new ASSPs, the VSC7460 Jaguar CE switch, the VSC7462 LynX CE switch, and the VSC7364 CE-MaX-24 MAC/switch, bring the full range of CE functions to high-speed Ethernet switches.

Accordingly, each chip has a service-aware classifier that can manage as many as 4000 services, each with its own QOS treatment, DE (discard-eligible) marking, color, policing, OAM (operations/administration/management), performance monitoring, and timing support through IEEE 1588 Version 2. The chips provide advanced QOS and MEF (Metro Ethernet Forum) policing based on a shared 32-Mbit buffer. They also have statistics counters; Ethernet OAM for all 4000 services; and support for 802.1ag, 802.3, Y.1731, and MEF-16 performance assurances.

The chips differ in CPU and I/O complements. The Jaguar has two 10-Gbps XAUI (10-Gbps attachment-unit-interface) and two 10-Gbps VAUI (5-Gbps-attachment-unit-interface) ports on one side and 24 multifunction SGMII (serial-gigabit-media-independent-interface)/SERDES (serializer/deserializer)/100BaseFX ports on the other. The LynX has just half as many of each. Both devices include a 400-MHz MIPS24KEc processor core.

The CE-MaX chip, which operates with an ASIC or an FPGA, uses two XAUI ports and a host interface to attach to the other chip and provides the full 24 SGMIIs plus two more XAUI ports downstream. The CE-MaX has no on-chip CPU. All three chips will be available in 27×27-mm HSBGA packages, and all are scheduled to become available for sampling in the second quarter. by Ron Wilson, Executive Editor -- EDN,


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