One-stop shop provides easy-to-use USB 3.0 IP

When looking to support its customers' adoption of the new emerging USB (Universal Serial Bus) standard, the Synopsys DesignWare SuperSpeed USB 3.0 IP (intellectual-property) engineering team wanted to ensure interoperability and ease of use by providing a single-vendor approach—from instantiation of the on-chip IP through certification and test.

The approach optimizes both area and performance. For example, it requires only one external reference-clock input and one external calibration resistor, which the high-speed and SuperSpeed operational modes share. In addition, the IP is compatible with a range of technology nodes—from the most advanced processes to older ones more suitable for low-volume or cost-sensitive applications.

Gervais Fong, product-marketing manager, cites some challenges and motivations for the team's approach. He notes that high-speed USB 2.0 runs at 480 Mbps, whereas SuperSpeed USB 3.0 runs at 5 Gbps. “The USB 3.0 specification includes the requirement to support all four USB speeds—low speed, full speed, high speed, and now the new SuperSpeed,” he says. “We find from an IP perspective that providing a complete solution to customers instead of giving them individual blocks makes it easier for them to integrate and provides faster time to market at lower cost. At the system level, we provide a complete USB solution consisting of the PHY [physical layer], the controller, the verification IP, and the reference drivers. We try to be the one-stop shop to make it easy for the design engineers to quickly and successfully implement USB 3.0 in their ASIC designs.”

Robert Lefferts, R&D director at the company, says that Synopsys also focuses on applying the resources and extra time and effort necessary to take the IP through certification and compliance testing. Combining certain functions expedites this process. “If we broke apart the SuperSpeed functionality from the standard USB 2 functionality, we couldn't follow through,” he says. “Attaching all the functionality together into one solution was a fairly big undertaking, but it helped get a complete solution that we can verify. One of the first things we looked at was crosstalk through the connector. How much margin would we need to take into account to handle that additional crosstalk of combining the 480-Mbps and 5-Gbps functions?” If the team had just broken the problem in half, he says, the customer would have had to worry about the answer to that question later.

Subramaniam Aravindhan, R&D manager at the company, comments on the USB 3.0 controller: “If you have separate 2.0 and 3.0 controllers, you need to have two subsystems—two bus interfaces—and that increases integration and verification costs. One major concern is software drivers. If you have a 2.0 programming model that is different from the 3.0 [model], you need to write different software drivers, and you need to validate the two drivers. Having a combined software model for 2.0 and 3.0 created a large initial effort for us, but, from the long-term point of view, it's a clean, complete, single solution.”

Lefferts cites one challenge of combining functions into one device. “One of the logistical problems for us was that the project involved design teams at seven locations.” Synopsys had to orchestrate those teams, which were in the United States, Canada, India, and Armenia, to deliver the final product.

Working out the logistics had a beneficial result, explains Lefferts. Two years ago, IP teams didn't tend to overlap. For example, USB 2.0 and high-speed SERDES (serializer/deserializer) teams were relatively isolated. “As a result of trying to go after a full solution for USB 3.0, all those barriers are down,” he says. “If customers have an issue, it doesn't matter whether it's on the high-speed 480-Mbps or SuperSpeed 5-Gbps side. There are people they can call now that understand both.”

Lefferts also addresses test issues. “The other feature we've implemented in the USB 3.0 solution came out of some of the work we've done on some of our other standards-based IP,” he says. “A lot of our customers for PCIe [Peripheral Component Interconnect Express] started out working with PCI at much lower frequencies. They had never worked with anything over a gigabit per second, and, when they went to PCIe Generation 1 at 2.5 Gbps, there was obviously a learning curve from a signal-integrity perspective. So we build our IP with diagnostic and debug capabilities to help them isolate problems. In this case, we are working with customers that were working at 480 Mbps and now are working at 5 Gbps. They might not even own a real-time scope that's even capable of looking at the signal. What we've done on our SERDES in general is to provide functions to be able to help separate where the problems are—whether it's a signal integrity-issue or it's a functional issue. We try to make our IP not only easy to use and integrate but also easy to debug so you can isolate and work on problems very quickly.”

Lefferts points out that manufacturers tend to implement other high-speed serial-I/O standards in advanced process technologies, whereas they may deploy USB 3.0, which provides a high-speed interface to some of the lowest-cost electronics devices available, on older process nodes. Consequently, the team had to address many technology nodes in a short period of time. Synopsys now has customers who have first silicon back and who will be taping out for volume production this year. By Rick Nelson, Editor-in-Chief -- EDN,

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